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CY29773
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Features
* * * * * * * * * * * * * * * Output frequency range: 8.33 MHz to 200 MHz Input frequency range: 6.25 MHz to 125 MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs 2% max Output duty cycle variation 12 Clock outputs: drive up to 24 clock lines One feedback output Three reference clock inputs: LVPECL or LVCMOS 300-ps max output-output skew Phase-locked loop (PLL) bypass mode Spread AwareTM Output enable/disable Pin-compatible with MPC9773 and MPC973 Industrial temperature range: -40C to +85C 52-pin 1.0-mm TQFP package
Description
The CY29773 is a low-voltage high-performance 200-MHz PLL-based zero delay buffer designed for high speed clock distribution applications. The CY29773 features one LVPECL and two LVCMOS reference clock inputs and provides 12 outputs partitioned in three banks of four outputs each. Each bank divides the VCO output per SEL(A:C) settings (see Table 2. Function Table (Configuration Controls)). These dividers allow output-to-input ratios of 8:1, 6:1, 5:1, 4:1, 3:1, 8:3, 5:2, 2:1, 5:3, 3:2, 4:3, 5:4, 1:1, and 5:6. Each LVCMOS-compatible output can drive 50 series- or parallel-terminated transmission lines. For series-terminated transmission lines, each output can drive one or two traces, giving the device an effective fanout of 1:24. The PLL is ensured stable, given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies, from 8 MHz to 200 MHz. For normal operation, the external feedback input FB_IN is connected to the feedback output FB_OUT. The internal VCO is running at multiples of the input reference clock set by the feedback divider (see Table 1. Frequency Table). When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply.
Block Diagram
Pin Configuration
PECL_CLK PECL_CLK# VCO_SEL PLL_EN REF_SEL DQ TCLK0 TCLK1 TCLK_SEL FB_IN DQ Sync Frz 0 1 Phase Detector LPF VCO 0 1 Sync Frz QA0 QA1 QA2 QA3 QB0 QB1 FB_SEL2 QB2 QB3
VCO_SEL
VDDQA
VDDQA
SELA0
SELA1
SELB0
SELB1
52 51 50 49 48 47 46 45 44 43 42 41 40 A V SS MR#/OE SCLK SDA TA FB_SEL2 PLL_EN REF_SEL TCLK_SEL TCLK0 TCLK1 PECL_CLK PECL_CLK# A V DD 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 V SS QB0 V DDQB QB1 V SS QB2 V DDQB QB3 FB_IN V SS FB_OUT V DD FB_SEL0
VSS
QA0
C Y29773
QA1
VSS
QA2
QA3
MR#/OE Power-On Reset SELA(0,1) SELB(0,1) SELC(0,1) FB_SEL(0,1) SCLK SDATA INV_CLK Output Disable Circuitry 12 2 2 2 2 /4, /6, /8, /10 Sync Pulse Data Generator DQ /2 0 1 DQ DQ /4, /6, /8, /12 /4, /6, /8, /10 /2, /4, /6, /8 DQ
Sync Frz
QC0 QC1
Sync Frz Sync Frz Sync Frz
QC2 QC3
14 15 16 17 18 19 20 21 22 23 24 25 26
INV_CLK
VSS
QC3
VDDQC
QC2
SELC1
SELC0
QC1
VDDQC
QC0
VSS
SYNC
FB_SEL1
FB_OUT
SYNC
Cypress Semiconductor Corporation Document #: 38-07573 Rev. **
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised August 27, 2003
CY29773
Pin Description [1]
Pin 11 12 9 10 44,46,48,50 32,34,36,38 16,18,21,23 29 31 Name PECL_CLK PECL_CLK# TCLK0 TCLK1 QA(3:0) QB(3:0) QC(3:0) FB_OUT FB_IN I/O I, PU I I, PU I, PU O O O O I, PU Type LVPECL LVPECL Description LVPECL reference clock input. LVPECL reference clock input.
LVCMOS LVCMOS/LVTTL reference clock input. LVCMOS LVCMOS/LVTTL reference clock input. LVCMOS Clock output bank A. LVCMOS Clock output bank B. LVCMOS Clock output bank C. LVCMOS Feedback clock output. Connect to FB_IN for normal operation. LVCMOS Feedback clock input. Connect to FB_OUT for normal operation. This input should be at the same voltage rail as input reference clock. See Table 1. Frequency Table. LVCMOS Synchronous pulse output. This output is used for system synchronization. LVCMOS PLL enable/bypass input. When Low, PLL is disabled/bypassed and the input clock connects to the output dividers. LVCMOS Master reset and Output enable/disable input. See Table 2. Function Table (Configuration Controls). LVCMOS LVCMOS Clock reference select input. See Table 2. Function Table (Configuration Controls). LVCMOS LVCMOS/LVPECL Reference select input. See Table 2. Function Table (Configuration Controls). LVCMOS VCO Operating frequency select input. See Table 2. Function Table (Configuration Controls). LVCMOS QC(2,3) Phase selection input. See Table 2. Function Table (Configuration Controls). LVCMOS Feedback divider select input. See Table 6. LVCMOS Frequency select input, Bank A. See Table 3. Function Table (Bank A). LVCMOS Frequency select input, Bank B. See Table 4. Function Table (Bank B). LVCMOS Frequency select input, Bank C. See Table 5. Function Table (Bank C). LVCMOS Serial clock input. LVCMOS Serial data input. VDD VDD VDD VDD VDD Ground Ground 2.5V or 3.3V Power supply for bank A output clocks.[2,3] 2.5V or 3.3V Power supply for bank B output clocks.[2,3] 2.5V or 3.3V Power supply for bank C output clocks.[2,3] 2.5V or 3.3V Power supply for PLL.[2,3] 2.5V or 3.3V Power supply for core and inputs.[2,3] Analog Ground. Common Ground.
25 6 2 8 7 52 14 5,26,27 42,43 40,41 19,20 3 4 45,49 33,37 22,17 13 28 1
SYNC PLL_EN MR#/OE TCLK_SEL REF_SEL VCO_SEL INV_CLK
O I, PU I, PU I, PU I, PU I, PU I, PU
FB_SEL(2:0) I, PU SELA(1,0) SELB(1,0) SELC(1,0) SCLK SDATA VDDQA VDDQB VDDQC AVDD VDD AVSS I, PU I, PU I, PU I, PU I, PU Supply Supply Supply Supply Supply Supply Supply
15,24,30,35,39,47,51 VSS
Notes: 1. PU = Internal pull up, PD = Internal pull down. 2. A 0.1-F bypass capacitor should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins their high frequency filtering characteristics will be cancelled by the lead inductance of the traces. 3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, and VDDQC power supply pins.
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CY29773
Table 1. Frequency Table Feedback Output Divider /4 /6 /8. /10 /12 /16 /20 /24 /32 /40 VCO Input Clock * 4 Input Clock * 6 Input Clock * 8 Input Clock * 10 Input Clock * 12 Input Clock * 16 Input Clock * 20 Input Clock * 24 Input Clock * 32 Input Clock * 40 Input Frequency Range (AVDD = 3.3V) 50 MHz to 125 MHz 33.3 MHz to 83.3 MHz 25 MHz to 62.5 MHz 20 MHz to 50 MHz 16.6 MHz to 41.6 MHz 12.5 MHz to 31.25 MHz 10 MHz to 25 MHz 8.3 MHz to 20.8 MHz 6.25 MHz to 15.625 MHz 5 MHz to 12.5 MHz Input Frequency Range (AVDD = 2.5V) 50 MHz to 95 MHz 33.3 MHz to 63.3 MHz 25 MHz to 47.5 MHz 20 MHz to 38 MHz 16.6 MHz to 31.6 MHz 12.5 MHz to 23.75 MHz 10 MHz to19 MHz 8.3 MHz to 15.8 MHz 6.25 MHz to 11.8 MHz 5 MHz to 9.5 MHz
Table 2. Function Table (Configuration Controls) Control REF_SEL TCLK_SEL VCO_SEL PLL_EN INV_CLK MR#/OE Default 1 1 1 1 1 1 TCLK0, TCLK1 TCLK0 VCO/2 (low input frequency range) Bypass mode, PLL disabled. The input clock connects to the output dividers QC2 and QC3 are in phase with QC0 and QC1 0 PECL_CLK TCLK1 VCO/1 (high input frequency range) PLL enabled. The VCO output connects to the output dividers QC2 and QC3 are inverted (180 phase shift) with respect to QC0 and QC1 1
Outputs enabled Outputs disabled (three-state) and reset of the device. During reset/output disable the PLL feedback loop is open and the VCO running at its minimum frequency. The device is reset by the internal power-on reset (POR) circuitry during power-up. Table 5. Function Table (Bank C) QA(0:3) /8 /12 /16 /24 /4 /6 /8 /12 VCO_SEL 0 0 0 0 1 1 1 1 SELC1 0 0 1 1 0 0 1 1 SELC0 0 1 0 1 0 1 0 1 QC(0:3) /4 /8 /12 16 /2 /4 /6 /8
Table 3. Function Table (Bank A) VCO_SEL 0 0 0 0 1 1 1 1 SELA1 0 0 1 1 0 0 1 1 SELA0 0 1 0 1 0 1 0 1
Table 4. Function Table (Bank B) VCO_SEL 0 0 0 0 1 1 1 1 SELB1 0 0 1 1 0 0 1 1 SELB0 0 1 0 1 0 1 0 1 QB(0:3) /8 /12 /16 /20 /4 /6 /8 /10
Table 6. Function Table (FB_OUT) VCO_SEL FB_SEL2 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 FB_SEL1 0 0 1 1 0 0 1 1 0 FB_SEL0 0 1 0 1 0 1 0 1 0 FB_OUT /8 /12 /16 /20 /16 /24 /32 /40 /4
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CY29773
Table 6. Function Table (FB_OUT) (continued) 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 /6 /8 /10 /8 /12 /16 /20
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CY29773
Absolute Maximum Conditions
Parameter VDD VDD VIN VOUT VTT LU RPS TS TA TJ OJC OJA ESDH FIT Description DC Supply Voltage DC Operating Voltage DC Input Voltage DC Output Voltage Output termination Voltage Latch-up Immunity Power Supply Ripple Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Failure in Time Manufacturing test Functional Ripple Frequency < 100 kHz Non-functional Functional Functional Functional Functional 2000 10 -65 -40 200 Functional Relative to VSS Relative to VSS Condition Min. -0.3 2.375 -0.3 -0.3 Max. 5.5 3.465 VDD + 0.3 VDD + 0.3 VDD / 2 - 150 +150 +85 +150 23 55 Unit V V V V V mA mVp-p C C C C/W C/W V ppm
DC Electrical Specifications (VDD = 2.5V 5%, TA = -40C to +85C)
Parameter VIL VIH VPP VCMR VOL VOH IIL IIH IDDA IDDQ IDD CIN ZOUT Description Input Voltage, Low Input Voltage, High Peak-Peak Input Voltage Common Mode Range[4] Output Voltage, Low
[5]
Condition LVCMOS LVCMOS LVPECL LVPECL IOL = 15 mA IOH = -15 mA VIL = VSS VIL = VDD AVDD only All VDD pins except AVDD Outputs loaded @ 100 MHz
Min. - 1.7 250 1.0 - 1.8 - - - - - - 14
Typ. - - - - - - - - 5 - 135 4 18
Max. 0.7 VDD+0.3 1000 VDD - 0.6 0.6 - -100 100 10 8 - - 22
Unit V V mV V V V A A mA mA mA pF
Output Voltage, High[5] Input Current, Low[5] Input Current, High[6] PLL Supply Current Quiescent Supply Current Dynamic Supply Current Input Pin Capacitance Output Impedance
DC Electrical Specifications (VDD = 3.3V 5%, TA = -40C to +85C)
Parameter VIL VIH VPP VCMR VOL VOH Description Input Voltage, Low Input Voltage, High Peak-Peak Input Voltage Common Mode Range[4] Output Voltage, Low[5] Output Voltage, High[5] Low[6 LVCMOS LVCMOS LVPECL LVPECL IOL = 24 mA IOL = 12 mA IOH = -24 mA Condition Min. - 2.0 250 1.0 - - 2.4 Typ. - - - - - - - Max. 0.8 VDD+0.3 1000 VDD - 0.6 0.55 0.30 - V Unit V V mV V V
IIL Input Current, VIL = VSS - - -100 A Notes: 4. VCMR (DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the VCMR range and the input swing is within the VPP (DC) specification. 5. Driving one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 series terminated transmission lines. 6. Inputs have pull-up or pull-down resistors that affect the input current. Document #: 38-07573 Rev. ** Page 5 of 12
CY29773
DC Electrical Specifications (VDD = 3.3V 5%, TA = -40C to +85C) (continued)
Parameter IIH IDDA IDDQ IDD CIN ZOUT Description Input Current, High[6] PLL Supply Current Quiescent Supply Current Dynamic Supply Current Input Pin Capacitance Output Impedance Condition VIL = VDD AVDD only All VDD pins except AVDD Outputs loaded @ 100 MHz Min. - - - - - 12 Typ. - 5 - 225 4 15 Max. 100 10 8 - - 18 Unit A mA mA mA pF
AC Electrical Specifications (VDD = 2.5V 5%, TA = -40C to +85C)[7]
Parameter fVCO fin Description VCO Frequency Input Frequency /4 Feedback /6 Feedback /8 Feedback /10 Feedback /12 Feedback /16 Feedback /20 Feedback /24 Feedback /32 Feedback /40 Feedback Bypass mode (PLL_EN = 0) frefDC VPP VCMR tr , tf fMAX Input Duty Cycle Peak-Peak Input Voltage Common Mode Range[8] TCLK Input Rise/FallTime Maximum Output Frequency LVPECL LVPECL 0.7V to 1.7V /2 Output /4 Output /6 Output /8 Output /10 Output /12 Output /16 Output /20 Output /24 Output fSCLK DC tr , tf t() Serial Clock Frequency Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) fMAX < 100 MHz fMAX > 100 MHz 0.6V to 1.8V TCLK to FB_IN PCLK to FB_IN Condition Min. 200 50 33.3 25 20 16.6 12.5 10 8.3 6.25 5 0 25 500 1.2 - 100 50 33.3 25 20 16.6 12.5 10 8.3 - 47.5 45 0.1 -125 -125 Typ. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Max. 380 95 63.3 47.5 38 31.6 23.75 19 15.8 11.8 9.5 200 75 1000 VDD - 0.6 1.0 190 95 63.3 47.5 38 31.6 23.75 19 15.8 20 52.5 55 1.0 125 125 ns ps MHz % % mV V ns MHz Unit MHz MHz
Notes: 7. AC characteristics apply for parallel output termination of 50 to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed by characterization and are not 100% tested. 8. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
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CY29773
AC Electrical Specifications (VDD = 2.5V 5%, TA = -40C to +85C)[7]
Parameter tsk(O) Description Output-to-Output Skew Condition Skew within Bank A Skew within Bank B Skew within Bank C tsk(B) tPLZ, HZ tPZL, ZH BW Bank-to-Bank Skew Output Disable Time Output Enable Time PLL Closed Loop Bandwidth (-3dB) /4 Feedback /6 Feedback /8 Feedback /10 Feedback /12 Feedback /16 Feedback /20 Feedback tJIT(CC) Cycle-to-Cycle Jitter Same frequency (125 MHz) RMS (1) Same frequency Multiple frequencies tJIT(PER) Period Jitter Same frequency (125 MHz) RMS (1) Same frequency Multiple frequencies tJIT() tLOCK I/O Phase Jitter Maximum PLL Lock Time Min. - - - - - - - - - - - - - - - - - - - - - Typ. - - - - - - 1.3 - 2.0 0.7 - 1.3 0.9 - 1.3 0.6 - 1.1 0.6 - 0.9 0.4 - 0.6 0.6 - 0.9 7 - - 6 45 - - - Max. 75 100 150 400 10 10 - - - - - - - 30 150 435 30 75 235 150 1 ps ms ps ps ps ns ns MHz Unit ps
AC Electrical Specifications (VDD = 3.3V 5%, TA = -40C to +85C)[7]
Parameter fVCO fin Description VCO Frequency Input Frequency /4 Feedback /6 Feedback /8 Feedback /10 Feedback /12 Feedback /16 Feedback /20 Feedback /24 Feedback /32 Feedback /40 Feedback Bypass mode (PLL_EN = 0) frefDC VPP VCMR tr , tf Input Duty Cycle Peak-Peak Input Voltage Common Mode Range[8] TCLK Input Rise/FallTime LVPECL LVPECL 0.8V to 2.0V Condition Min. 200 50 33.3 25 20 16.6 12.5 10 8.3 6.25 5 0 25 500 1.2 - Typ. - - - - - - - - - - - - - - - - Max. 500 125 83.3 62.5 50 41.6 31.25 25 20.8 15.625 12.5 200 75 1000 VDD-0.9 1.0 % mV V ns Unit MHz MHz
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CY29773
AC Electrical Specifications (VDD = 3.3V 5%, TA = -40C to +85C)[7]
Parameter fMAX Description Maximum Output Frequency Condition /2 Output /4 Output /6 Output /8 Output fMAX Maximum Output Frequency (continued) /10 Output /12 Output /16 Output /20 Output /24 Output fSCLK DC tr , tf t() tsk(O) Serial Clock Frequency Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) Output-to-Output Skew fMAX < 100 MHz fMAX > 100 MHz 0.55V to 2.4V TCLK to FB_IN, same VDD PCLK to FB_IN, same VDD Skew within Bank A Skew within Bank B Skew within Bank C tsk(B) tPLZ, HZ tPZL, ZH BW Bank-to-Bank Skew Output Disable Time Output Enable Time PLL Closed Loop Bandwidth (-3 dB) /4 Feedback /6 Feedback /8 Feedback /10 Feedback /12 Feedback /16 Feedback /20 Feedback tJIT(CC) Cycle-to-Cycle Jitter Same frequency (125 MHz) RMS (1) Same frequency Multiple frequencies tJIT(PER) Period Jitter Same frequency (125 MHz) RMS (1) Same frequency Multiple frequencies tJIT() tLOCK SYNC Output In situations where output frequency relationships are not integer multiples of each other the SYNC output provides a signal for system synchronization. The CY29773 monitors the relationship between the QA and the QC output clocks. It provides a low going pulse, one period in duration, one period prior to the coincident rising edges of the QA and QC outputs. I/O Phase Jitter Maximum PLL Lock Time I/O same VDD Min. 100 50 33.3 25 20 16.6 12.5 10 8.3 - 48 45 0.1 -125 -125 - - - - - - - - - - - - - - - - - -- - - - Typ. - - - - - - - - - - - - - - - - - - - - - 1.3-2.0 0.7-1.3 0.9-1.3 0.6-1.1 0.6-0.9 0.4-0.6 0.6-0.9 7 - - 6 45 - - - Max. 200 125 83.3 62.5 50 41.6 31.25 25 20.8 20 52 55 1.0 125 125 75 100 150 325 8 8 - - - - - - - 30 100 375 30 75 225 150 1 ps ms ps ps ps ns ns MHz ps ns ps MHz % MHz Unit MHz
The duration and the placement of the pulse depend on the higher of the QA and QC output frequencies. The following timing diagram illustrates various waveforms for the SYNC output. Note that the SYNC output is defined for all possible combinations of the QA and QC outputs even though under some relationships the lower frequency clock could be used as a synchronizing signal.
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CY29773
VCO 1:1 Mode QA QC SYNC 2:1 Mode QA QC SYNC 3:1 Mode QC QA SYNC 3:2 Mode QA QC SYNC 4:1 Mode QC QA SYNC 4:3 Mode QA QC SYNC 6:1 Mode QA QC SYNC
Figure 1.
Power Management The individual output enable/freeze control of the CY29773 allows the user to implement unique power management schemes into the design. The outputs are stopped in the logic `0' state when the freeze control bits are activated. The serial input register contains one programmable freeze enable bit for 12 of the 14 output clocks. The QC0 and FB_OUT outputs can not be frozen with the serial port, this avoids any potential lock up situation should an error occur in the loading of the serial Document #: 38-07573 Rev. **
data. An output is frozen when a logic `0' is programmed and enabled when a logic `1' is written. The enabling and freezing of individual outputs is done in such a manner as to eliminate the possibility of partial "runt" clocks. The serial input register is programmed through the SDATA input by writing a logic `0' start bit followed by 12 NRZ freeze enable bits. The period of each SDATA bit equals the period of the free running SCLK signal. The SDATA is sampled on the rising edge of SCLK. Page 9 of 12
CY29773
Start Bit D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
D0-D3 are the control bits for QA0-QA3, respectively D4-D7 are the control bits for QB0-QB3, respectively D8-D10 are the control bits for QC1-QC3, respectively D11 is the control bit for SYNC Figure 2.
Pulse Generator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm
RT = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 3. LVCMOS_CLK AC Test Reference for VDD = 3.3V/2.5V
Zo = 50 ohm Differential Pulse Generator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm RT = 50 ohm RT = 50 ohm
VTT
VTT
Figure 4. PECL_CLK AC Test Reference for VDD = 3.3V/2.5V
PECL_CLK PECL_CLK
VPP
VCMR
VDD
FB_IN
VDD/2
t()
GND
Figure 5. LVPECL Propagation Delay t(), Static Phase Offset
LVCMOS_CLK
VDD VDD/2 GND VDD
FB_IN
VDD/2
t()
GND
Figure 6. LVCMOS Propagation Delay t(), Static Phase Offset
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CY29773
VDD VDD/2
tP
T0
GND
DC = tP / T0 x 100%
Figure 7. Output Duty Cycle (DC)
VDD VDD/2 GND VDD VDD/2
tSK(O)
Figure 8. Output-to-Output Skew, tsk(O)
GND
Ordering Information
Part Number CY29773AI CY29773AIT 52-pin TQFP 52-pin TQFP - Tape and Reel Package Type Product Flow Industrial, -40C to +85C Industrial, -40C to 85C
Package Drawing and Dimension
52-Lead Thin Plastic Quad Flat Pack (10 x 10 x 1.0 mm) A52B
51-85158-**
Spread Aware is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07573 Rev. ** Page 11 of 12
(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY29773
Document History Page
Document Title:CY29773 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Document Number: 38-07573 REV. ** ECN No. 129007 Issue Date 09/02/03 Orig. of Change RGL New Data Sheet Description of Change
Document #: 38-07573 Rev. **
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